Datasheet
www.tektronix.com/oscilloscopes 33
Debugging Serial Buses in Embedded System Designs
Audio Buses
Background
I
2
S, or “I squared S”, stands for Inter-IC Sound. It was
originally developed by Philips in the mid-1980s to provide a
standardized communication path for digital audio signals in
consumer electronic devices such as CD players and digital
televisions. The consumer electronics market has continued
to evolve over the last 20 years and so have the applications
for the I
2
S bus. Today it’s commonly found in cell phones, MP3
players, set top boxes, professional audio equipment and
gaming systems to name a few.
How It Works
The I
2
S bus is a master/slave 3-wire serial communications
bus. The three signals are clock (SCK), word select (WS),
and data (SD). Typically, the transmitter is the Master and the
receiver is the Slave. However, in some cases, the receiver can
act as the Master by generating the clock and the word select
signals. Or the transmitter and the receiver can be controlled
by another device if desired. These configuration scenarios are
illustrated in Figure 45.
Serial data is transmitted in two’s complement with the most
significant bit (MSB) first. The MSB is transmitted first because
the transmitter and receiver may have different word lengths.
It isn’t necessary for the transmitter to know how many bits
the receiver can handle, nor does the receiver need to know
how many bits are being transmitted. When the system word
length is greater than the transmitter word length, the word
is truncated (least significant data bits are set to ‘0’) for data
transmission. If the receiver is sent more bits than its word
length, the bits after the least significant bit (LSB) are ignored.
On the other hand, if the receiver is sent fewer bits than its
word length, the missing bits are set to zero internally. And so,
the MSB has a fixed position, whereas the position of the LSB
depends on the word length. The transmitter always sends the
MSB of the next word one clock period after the WS changes.
Figure 45. Different I
2
S bus configurations.
TRANSMITTER
TRANSMITTER = MASTER
data SD
word select WS
clock SCK
RECEIVER TRANSMITTER
RECEIVER = MASTER
SD
WS
SCK
CONTROLLER = MASTER
RECEIVER
TRANSMITTER
SD
WS
SCK
RECEIVER
CONTROLLER