Datasheet

www.tektronix.com/bench 11
Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope
Next, the D input is checked for setup/hold violations. MSO
setup/hold triggering is configured for a 2 ns setup time and a
1 ns hold time to check for D input changes in the data valid
window around the rising clock edge.
Figure 22 shows a serious D input setup/hold violation. Cursor
‘a’ is located at the minimum 2 ns setup time before the rising
clock edge and cursor ‘b’ is located at the minimum 1 ns hold
time after the rising clock edge. The D input is required to be
stable during this 3 ns data valid window around the rising
clock edge. The D-Flip-Flop is not specified to work properly
with the D input changing in data valid window.
At this point in the verification process there are three
problems with the D-Flip-Flop operation and its signals. The
first problem is a non monotonic rising clock edge. The clock
circuit needs to be redesigned to have a better rising edge.
The second problem is the 74F74 is not correctly working with
D input setup times of 2 ns to 4.188 ns. This may be related
to the poor rising clock edge or the 74F74 is not meeting its
specifications. The third problem is the D input setup/hold
violation. The D input circuit needs to be redesigned so that it
does not change during the clock edge setup/hold window.
Using Wave Inspector
®
to Quickly Verify
ADC Outputs
In this example, the output range of a sensor’s data acquisition
system is verified with a fixed test ramp signal. The sensor
data acquisition system is an analog signal conditioning circuit
that feeds a 20 MS/s, 6-bit Analog to Digital Converter (ADC).
The ADC 6-bit data bus is valid on the ADC falling clock edge.
The test ramp signal at the acquisition system input should
produce a range of ADC values from 00 to 3F hex.
The MSO analog channel is connected to the signal
conditioning output which is also the ADC input. This provides
a quick check of the signal conditioning output and ADC
input signal. The MSO digital channel zero is connected
to the ADC clock output and digital channels one through
six are connected to the ADC 6-bit data bus as shown in
Figure 23. The MSO is set to trigger on the rising edge of
ADC input signal.
Figure 22. MSO triggering on the D-Flip-Flop data changing in the setup/hold window
between cursor ‘a’ and ‘b’ around the rising clock edge.
Acquisition System
Test Signal
Digital Bus
MSO D1-D6
Bus Clock
MSO D0
ADC Input
MSO Ch1
3F hex
00 hex
Signal
Conditioning
ADC
Figure 23. Verify sensor data acquisition system output range.