Datasheet

Application Note
www.tektronix.com/bench10
Figure 19 shows the MSO captured a Q output pulse width
that is less than 19.2 ns. Notice that this Q output pulse width
is less than the clock period. Analysis of the waveforms show
that the D input is high when the rising clock edge occurred.
The Q output low-to-high transition is correct but the following
high-to-low transition is an error in the D-Flip-Flop operation
because the transition is unrelated to a rising clock edge.
The analog channel is connected to the Q output to provide
additional insight into the problem as shown in Figure 20.
The Q output analog signal started to increase but shortly
thereafter it decreased. Notice the Q output analog signal did
not reach the normal analog logic high level before it dropped
back down.
From past debugging experiences this may be a metastable
glitch caused by a setup/hold timing violation of the D input in
regards to the clock edge.
In Figure 20, the D input setup time is 4.188 ns as measured
with the cursors. This setup time is twice as long as the
74F74’s 2 ns minimum setup time specification. But, the
74F74 is not operating correctly with the D input changing
4.188 ns before the clock edge.
The MSO triggering is changed to capture setup/hold
violations to determine how much setup time is needed for
this 74F74 to operate correctly. Figure 21 shows the Q output
correctly working with a 4.488 ns setup time between the
rising D input and the rising clock edge. Other acquisitions
show the Q output having occasional glitches when the setup
time is 4.188 ns or less.
Figure 19. D-Flip-Flop Q output error. Figure 20. D-Flip-Flop Q output error with analog insight.
Figure 21. D-Flip-Flop Q output correctly working with 4.488 ns setup time before the
rising clock edge.