User Manual 73A-270 Arbitrary Pulse/Pattern Generator Module 070-9148-03 This document supports firmware version 1.00 and above. Warning The servicing instructions are for use by qualified personnel only. To avoid personal injury, do not perform any servicing unless you are qualified to do so. Refer to the Safety Summary prior to performing service.
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WARRANTY Tektronix warrants that this product will be free from defects in materials and workmanship for a period of three (3) years from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product.
EC Declaration of Conformity We Tektronix Holland N.V. Marktweg 73A 8444 AB Heerenveen The Netherlands declare under sole responsibility that the 73A-270 meets the intent of Directive 89/336/EEC for Electromagnetic Compatibility.
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General Safety Summary Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it. Only qualified personnel should perform service procedures. While using this product, you may need to access other parts of the system. Read the General Safety Summary in other system manuals for warnings and cautions related to operating the system.
General Safety Summary Safety Terms and Symbols Terms in This Manual These terms may appear in this manual: WARNING. Warning statements identify conditions or practices that could result in injury or loss of life. CAUTION. Caution statements identify conditions or practices that could result in damage to this product or other property. Terms on the Product These terms may appear on the product: DANGER indicates an injury hazard immediately accessible as you read the marking.
VXIbus Radiated Emissions: VXIbus Conducted Emissions:
Appendix D: Performance Verification This procedure verifies the performance of the 73A-270 Arbitrary Pulse-Pattern Generator. It may be performed in your current VXIbus system if it meets the requirements described in Table A–2. Also, it is not necessary to complete the entire procedure if you are only interested in a specific performance area. Some tests depend on the correct operation of previously verified functions so it is best to perform the entire procedure in the order presented.
Appendix D: Performance Verification Prerequisites The test sequences in this procedure are a valid verification of the 73A-270 when the following requirements are met: H The 73A-270 has been calibrated within the last 12 months H The 73A-270 module covers are in place and the module is installed in an approved VXIbus mainframe according to the procedure in Section 2 of the Operating Manual H The 73A-270 has passed its power-on self test H The 73A-270 is operating in an ambient environment as specif
Appendix D: Performance Verification 73A-270-Under-Test Configuration In order to perform this verification procedure, the 73A-270-under-test must be installed in an approved VXIbus system. At a minimum, the system must contain the elements listed in Table A–2. Table A–2: Elements of a Minimum 73A-270 –Under-Test System Item Number and Description Minimum Requirements Example Purpose 1.
Appendix D: Performance Verification 73A-270 Test Record 73A-270 Serial Number: Temperature and Relative Humidity: Date of Last Calibration: Verification Performed by: Certificate Number: Date of Verification: VXIbus Interface Checks Logical Address, IEEE Address, Slot No., MFG., Model, etc.
Appendix D: Performance Verification 73A-270 Test Record (Cont.) TTL OUT B Checks Pulse Duration Multiplier Minimum Maximum 1000 × 100 ns 4,999.5 Hz 5,000.5 Hz 100 × 1 ms 4,999.5 Hz 5,000.5 Hz 10 × 10 ms 4,999.5 Hz 5,000.5 Hz 1 × 100 ms 4,999.5 Hz 5,000.5 Hz 2 × 100 ms 2,499.75 Hz 2,500.25 Hz 85.8585 ms ±20 ns . ms ±20 nss 42.4242 85.85848 ms 85.85852 ms 42.42418 ms 42.
Appendix D: Performance Verification 73A-270 Test Record (Cont.
Appendix D: Performance Verification Self Test Following the VXIbus system startup sequence, the green PWR light on the 73A-270 front panel indicates that all power supplies are operational. If the +5 V, –5.2 V, –2 V, ± 24 V or the internally regulated ± 20.9 V buses fail, or if the –2 V, +5 V, –5.2 V, or ± 24 V fuses open, the PWR light will be off. Additionally, the FAILED light will be on and SYSFAIL* will be asserted indicating a module failure.
Appendix D: Performance Verification VXIbus Interface This sequence verifies that the 73A-270 configures correctly and communicates properly with your system controller. Equipment Requirements Oscilloscope (item 1) Prerequisites All prerequisites listed on page 56 50 Coaxial Cable (item 5) 1. Send the appropriate commands to the Slot 0 device to get the primary/secondary GPIB address of the 73A-270, 73A-541, and VX4790A. Place these addresses into the IBCONF configurator for the VX270.
Appendix D: Performance Verification NOTE. Make sure the 73A-270 and the Slot 0 Resource Manager are set to the same INT LEVEL. Also, If an embedded controller is being used, follow the operating manual for displaying the state of the interrupt lines. (Observe 02 response) 4. Check for VXIbus Request True event by performing a serial poll and verify that the response byte is (i.e.
Appendix D: Performance Verification (Observe 100 ns ±10 ns pulse width) c. Verify the additional time base resolutions as directed in Table A–4 Table A–4: Time Base Resolution Verification Command to Send Pulse Width to Verify (step 2b repeated for table continuity) 100 ns ±10 ns 1 ms ±10 ns 10 ms ±10 ns 100 ms ±10 ns (Verify that the waveform stopped) 3.
Appendix D: Performance Verification Table A–5: Pulse Duration Multiplier Verification Multiplier / Resolution Verify Period and Duty Cycle IBWRT "0A0R10001L10004L0C0B" (step 3 repeated for table continuity) 1000 100 ns 5 kHz ±0.5 Hz, 50% ±0.1% IBWRT "1R0A1001L1004L0C0B" 100 1 ms 5 kHz ±0.5 Hz, 50% ±0.1% IBWRT "2R0A101L104L0C0B" 10 10 ms 5 kHz ±0.5 Hz, 50% ±0.1% IBWRT "3R0A11L14L0C0B" 1 100 ms 5 kHz ±0.5 Hz, 50% ±0.1% IBWRT "0A21L24L" 2 100 ms 2.5 kHz ±0.
Appendix D: Performance Verification e. Stop the counter/timer acquisition, read one response, and verify a return count of 42 events. (Observe return count of 42 events) f. Repeat the burst test sending the data list 21 times. (Observe return count of 21 events) 6. This completes the TTL OUT signal test sequence.
Appendix D: Performance Verification 3. To verify the BPLR pulse-pattern phase and ±2 V accuracy, set the 73A-270 to generate a continuous pulse-pattern square wave from both the TTL and the BPLR outputs with a 10 ms period and a bipolar amplitude of ±2.0V. Check that the BPLR OUT signal is in phase with the TTL OUT signal and that the amplitude is ±2.0 V ±2 mV. SET VX270 IBWRT "0S" or IBWRT "1S" (Select Ch-A or Ch-B) IBWRT "1R0A0C51L54L0B" IBWRT "20P-20N" (Verify ±2.0 V ±260 mV) 4.
Appendix D: Performance Verification Equipment Requirements Oscilloscope (item 1) Counter/Timer (item 3) 50 BNC Coaxial Cable, two required (item 5) Prerequisites All prerequisites listed on page 56 All previous Performance Verification Tests 1. Connect TTL OUT A to Ch-2 of the oscilloscope (1 M input impedance). 2.
Appendix D: Performance Verification Table A–6: (Cont.)VXIbus TTL Trigger Line Verification Ch. A triggered by Ch. B TTLTRG Line Change Setup, Restart Pattern, Verify 500 kHz Pulse-Pattern TTLTRG6* TTLTRG7* 4. Using the following commands, disable both channels from the TTLTRGX* lines and then resend the trigger pulse from channel B to restart the pulse-pattern from channel A.
Appendix D: Performance Verification (Verify a TTL high level) c. Retrigger the pulse-pattern several times and check after each start that the TTL OUT A signal level alternates between a TTL low level and a TTL high level. (Verify a TTL low level) (Verify a TTL high level) (Verify that the pulse-pattern stops) 7. Verify channel B operation with the VXIbus TTL Trigger Lines with the following steps: a.
Appendix D: Performance Verification Table A–7: (Cont.)VXIbus TTL Trigger Line Verification Ch. B triggered by Ch. A TTLTRG Line Change Setup, & Restart Pattern TTLTRG3* TTLTRG4* TTLTRG5* TTLTRG6* TTLTRG7* e. With the following commands, disable both channels from the TTLTRGX* lines and restart the channel A pulse pattern.
Appendix D: Performance Verification a. Program TTL OUT B to generate a continuous pulse pattern having a 10 ms active high level pulse with an active breakpoint followed by a 10 ms active low level pulse with an active breakpoint with the following steps: b. Check that TTL OUT B is held at a TTL high level, which demonstrates that the pattern stopped at the active high pulse breakpoint. c.
Appendix D: Performance Verification External Clock and Transmission In Progress This sequence verifies the high and low speed external clock inputs and the Transmission In Progress signal inputs on the front panel DB-25 connector.
Appendix D: Performance Verification e. Set the 73A-270 to divide the 1 MHz external clock source by 10 (10 ms resolution) and to set the pulse duration multiplier to 10 to generate a square wave with a 200 ms period (5 kHz) with the following steps: SET VX270 IBWRT "0S1R0A0M101L104L0C0B" (Verify 5 kHz waveform) f. Momentarily disconnect the SMB connector from the VX4790A and check that the 5 kHz pulse pattern is no longer present on TTL OUT A. 2.
Appendix D: Performance Verification b. Set the 73A-270 to generate a 500 Hz square wave and then stop the pulse pattern: (Verify a square wave) (Verify no pattern) c. Using the oscilloscope probe, check that S1 pin 2 (Transmission In Progress A, active high), is a TTL low level and that pin 3 (Transmission In Progress A, active low) is a TTL high level. d.
Appendix D: Performance Verification 76 73A-270 Arbitrary Pulse/Pattern Generator Module
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