User Manual

Dell
PowerEdge R710 Technical Guide 35
Chipset
Overview
The PowerEdge R710 planar incorporates the Intel
®
Xeon
®
5500 processor series chipset for I/O and processor
interfacing. This chipset is designed to support the Intel Xeon 5500 and 5600 processor series family, QuickPath
Interconnect, DDR3 memory technology, and PCI Express Generation 2. The chipset consists of the Intel 5500
chipset I/O Hub (IOH) and ICH9.
Intel I/O Hub (IOH)
The planar uses the Intel 5500 chipset IOH to provide a link between the Intel Xeon processor series 5500 and
5600 processor(s) and the I/O components. The main components of the IOH consist of two full-width
QuickPath Interconnect links (one to each processor), 36 lanes of PCI Express Gen2, a x4 Direct Media Interface
(DMI), and an integrated IOxAPIC.
IOH QuickPath Interconnect (QPI)
The QuickPath Architecture consists of serial point-to-point interconnects for the processors and the IOH. The
R710 has a total of three QuickPath Interconnect (QPI) links—one link connecting the processors, and multiple
links connecting both processors with the IOH. Each link consists of 20 lanes (full-width) in each direction with
a link speed of 6.4 GT/s. An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as
packets.
The QuickPath Architecture implemented in the IOH and processors features four layers:
• Physical layer—This layer consists of the actual connection between components. It supports Polarity
Inversion and Lane Reversal for optimizing component placement and routing.
• Link layer—This layer is responsible for flow control and the reliable transmission of data.
• Routing layer—This layer is responsible for the routing of QPI data packets.
• Protocol layer—This layer is responsible for high-level protocol communications, including the
implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol.
IOH PCI Express
PCI Express is a serial point-to-point interconnect for I/O devices. PCIe Generation 2 doubles the signaling bit
rate of Generation 1 from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports are backwards-compatible with
Gen1 transfer rates.
The IOH has 36 PCI Express lanes. The lanes are partitioned as two x2 PCI Express Gen2 ports and eight x4 PCI
Express Gen2 ports. The x2 ports can be combined as a x4 link; however, this x4 link cannot be combined with
any of the other x4 ports. Two neighboring x4 ports can be combined as a x8 link, and both resulting x8 links
can combine to form a x16 link.