User's Manual

36 DRAFT P440 Data Sheet / User Guide
Fig. 23: GPIO and associated connector and pin locations
As of this date, there is currently no software support (i.e. API commands) for controlling the state of
the GPIOs. Similarly, the function of the SPI lines is currently fixed such that these lines can only be
used for SPI. Time Domain expects to provide expanded support for GPIOs in an upcoming
software release.
4.6 Antenna Ports
The P440 has two antenna ports, designated Port A and Port B. The connector used on each port is a
standard polarity female SMA connector (Digi-Key part number J801-ND). The two ports enable
single and dual antenna modes of operation.
An RF transfer switch on the P440 controls how the RF electronics are connected to the SMA
connector. Normal operation can be defined as:
1) Transmit/Receive on Port A
2) Transmit on A, Receive on B
3) Transmit/Receive on Port B
4) Transmit on B, Receive on A
RF energy generated by the UWB FIFE chip for radiation from the antenna will travel through the RF
transfer switch on its way to the antenna. In doing so, some of the energy will leak through the
J11 - Locking
1 SPI_MOSI
2 SPI_INT
3 SPI_MISO
7 SPI_CLK
9 SPI_CS
4 FPGA_GPIO_1_3.3V
6 FPGA_GPIO_2_3.3V
11 ARM_GPIO_0_3.3V
15 FPGA_GPIO_3_3.3V
J10 - User Mezzanine
1 SPI_MOSI
3 SPI_MISO
4 SPI_INT
6 FPGA_GPIO_1_3.3V
7 SPI_CLK
8 FPGA_GPIO_2_3.3V
9 SPI_CS
11 ARM_GPIO_0_3.3V
15 ARM_GPIO_1_3.3V
J8 - Ethernet Mezzanine
17 ARM_GPIO_0_1.8V
18 ARM_GPIO_1_1.8V
J6 - Factory Mezzanine
12 FPGA_GPIO_1_1.8V
18 FPGA_GPIO_0_1.8V
20 ARM_GPIO_2_3.3V