User's Manual

P330 Data Sheet / User Guide 25
DRAFT
CSn
CLK
MOSI
MISO 7 6 5 4 3 2 1 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
7
Bit 0
0
Fig. 4-11: Signaling timing diagram
The master drives the SPI chip-select low (CSn in above figure) and shifts an 8-bit command,
possibly followed by data. The first bit (MSb) of a command is always set. If the second bit is set,
then it is a read command, otherwise it is a write command. The commands are listed below in
Figure 4-12. The chip-select must stay active-low for the entire transaction, which is required to be
on 8-bit boundaries. This and other timing diagrams are shown in Figure 4-13. Timing constraints
are shown in Figure 4-14.
Command
Function
Command Format
Response Format
0x80
Write to slave input FIFO
Command
followed by data
N/A
0xC0
Read from slave output
FIFO
Command
Slave output FIFO data
0xC2
Read slave output FIFO
byte count
Command
Two bytes: MSB followed by LSB
Fig. 4-12: SPI command structure
CSn
Clk
MOSI
MISO
8-bit command (0xC2)
Response Byte 1 (MSB) Response Byte 2 (LSB)
Don’t Care
Don’t Care
Don’t Care
Read slave output FIFO byte count
CSn
Clk
MOSI
MISO
8-bit command
Data Byte 1
Data Byte 2
Don’t Care
Don’t Care
Don’t Care
Write to slave input FIFO
Data Byte N
Don’t Care
Fig. 4-13: Timing diagrams