User's Manual

24 P330 Data Sheet / User Guide
DRAFT
While most users will connect to the serial port through either J11 or J10 doing so requires the
construction of a dedicated cable or interface. To use the serial interface directly, the user can
connect directly to J7 using a standard cable available from a number of sources including the
following:
 FTDI (part number TTL-232R-3v3) or
 Digikey (part number 768-1015-ND www.digikey.com).
4.4.3 SPI
The SPI interface is designed to operate at a maximum clock rate of 16.0 MHz with signals operating
at 3.3V TTL levels. The actual throughput of the link is limited by the various communications
overheads. However, transfer rates of 6-7 Mbps have been achieved using an un-optimized system.
The SPI interface allows the user to control the P330 with a co-located single board computer. Since
the operating speed of the link is subject to noise and line capacitance, the length of the SPI wiring
should be kept as short as possible. When operating the SPI interface at a maximum rate of 16Mhz,
the cable length should be no longer than a few inches (10-15cm). The exact length needs to be
confirmed empirically. If, for a given length of cable, the link experiences communications
problems, then the user should reduce the SPI clock rate.
The SPI port consists of five signals. Four of these are the typical SPI signals: CLK, CSn, MOSI, and
MISO, each with a 100k pull-up resistor to 3.3 V. The fifth signal (INT) is active-high and is used to
indicate that data exists in the slave output FIFO. The INT signal does not have a pull-up resistor and
is not driven during initial power-up. The signals are illustrated in Figure 4-10. The SPI slave RX
and TX FIFOs are 4k x 8.
Fig. 4-10: SPI interconnect signals
The SPI port uses 8-bit bytes sent MSb first. The CLK idle state is high. The data is propagated on
the falling-edge (leading-edge) of clock and sampled on the rising-edge (trailing-edge) of clock as
shown below in Figure 4-11:
Master
Slave
CLK
CSn
MOSI
MISO
INT