User's Manual

BM63SPKA1MGA
ISSC Confidential (Version: 1.2) - 6 - 10/15/2014
Pin No.
Pin type
Name
Description
Line-in Detector
47
I/O
P05
GPIO, default pull-high input
Charger Status
48
P
GND
Ground Pin
49
P
ANT1
Antenna modification point
50
P
ANT2
Antenna modification point
51
P
ANT3
Antenna modification point
Block Diagram
Common RAM
BT 3.0 Digital Core
ROM
Interrupts
BUS
HCI/UART
GPIOs (Buttons)
I2C (GPIOs or H/W)
RAM
MCU Core
DSP Core
Memory Controller
DMA Controller
Modem + MAC
DSP ROM/RAM
PMU
Battery Charger
LDO
SAR_ADC
LED Driver * 2
BUCK
Power Switch
BT 3.0
Transceiver
Synthesizer
RF Transmitter
RF Receiver
XTAL + POR
Misc. PMU logic
EEPROM
Buttons
ULPC 32KHz
SPI
Flash
Audio Codec
Stereo DAC
Stereo ADC
Anti-Pop
Audio Digital Core
I2S/PCM
Module
External
MCU