User's Manual

BM63SPKA1MGA
ISSC Confidential (Version: 1.2) - 4 - 10/15/2014
Pin Definition for Flash module
Pin No.
Pin type
Name
Description
1
I
DR0
I2S interface: Digital Left/Right Data from ADC
2
O
RFS0
I2S interface: DAC Left/Right Clock
3
O
SCLK0
I2S interface: Bit Clock
4
O
DT0
I2S interface: Digital Left/Right Data to DAC
5
O
AOHPR
R-channel analog headphone output
6
O
AOHPM
Headphone common mode output/sense input.
7
O
AOHPL
L-channel analog headphone output
8
I
MICN1
MIC 1 mono differential analog negative input
9
I
MICP1
MIC 1 mono differential analog positive input
10
P
MICBIAS
Electric microphone biasing voltage
11
I
AIR
R-channel single-ended analog input
12
I
AIL
L-channel single-ended analog input
13
I/O
P12
GPIO, default pull-high input
1. KEY PIN for FT Test
2. EEPROM clock SCL
14
I/O
P13
GPIO, default pull-high input
1. KEY PIN for FT Test
2. EEPROM data SDA
15
I
RST_N
KEY PIN for FT Test
System Reset Pin (Low active)
16
I/O
P01
GPIO, default pull-high input
BAT_CHK_EN
17
I/O
P24
GPIO, default pull-high input
1. KEY PIN for FT Test
2. System Configuration:
H: Boot Mode
L: Boot Mode with P2_0 low combination
18
I/O
P04
GPIO, default pull-high input.
19
I/O
P15
GPIO, default pull-high input
20
I
HCI_RXD
KEY PIN for FT Test
1-bit serial data received from MCU through UART
21
O
HCI_TXD
KEY PIN for FT Test
1-bit serial data transmitted to MCU through UART
22
P
CODEC_VO
3.1V LDO output for CODEC power
23
P
VDD_IO
I/O power supply input