Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 78 of 143
2.3.1.2 Guidelines for PWR_ON layout design
The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to switch on
the TOBY-L3 series modules. It is required to ensure that the voltage level is well defined during operation
and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on
request.
2.3.2 Module reset (RESET_N)
2.3.2.1 Guidelines for RESET_N circuit design
TOBY-L3 series RESET_N line is equipped with an internal pull-up to the V_INT supply as shown in Figure
30. An external pull-up resistor is not required.
If connecting the RESET_N input to a push button, the pin will be externally accessible on the application
device. According to the EMC/ESD requirements of the application, an additional ESD protection device (e.g.
the EPCOS CA05P4S14THSG varistor) should be provided close to the accessible point on the line connected
to this pin, as shown in Figure 30 and Table 25.
☞ The ESD sensitivity rating of the RESET_N pin is 1 kV (HBM according to JESD22-A114). A higher
protection level can be required if the line is externally accessible on the application board, e.g. if an
accessible push button is directly connected to the RESET_N pin, and it can be achieved by mounting
an ESD protection (e.g. EPCOS CA05P4S14THSG varistor) close to the accessible point.
An open drain output is suitable to drive the RESET_N input from an application processor as it is equipped
with an internal pull-up to V_INT supply, as shown in Figure 30.
A compatible push-pull output of an application processor can also be used. In any case, take care to set
the correct level in all the possible scenarios to avoid an inappropriate module reset.
TOBY-L3 series
5
VCC_INT
23
RESET_N
Reset
push button
ESD
Open
Drain
Output
Application
Processor
TOBY-L3 series
5
VCC_INT
23
RESET_N
TP
TP
200 k
200 k
Figure 30: RESET_N application circuits using a push button and an open drain output of an application processor
Reference
Description
Part Number - Manufacturer
ESD
Varistor for ESD protection
CT0402S14AHSG - EPCOS
Table 25: Example of ESD protection component for the RESET_N application circuits