Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 49 of 143
1.9.3 SPI interfaces
1.9.3.1 SPI0 interface
The SPI0 1.8 V Serial Peripheral Interface supports communication with an external SPI slave devices, with
the module acting as SPI master, by means of the open CPU API, with the following pins:
SPI_MOSI pin, SPI0 Master Output Slave Input (module output)
SPI_MISO pin, SPI0 Master Input Slave Output (module input)
SPI_SCLK pin, SPI0 Serial Clock (module output)
SPI_CS pin, SPI0 Chip Select 0 (module output)
The SPI Serial Clock signal work on the frequency at 960KHz, 4.8MHz, 9.6MHz, 16MHz, 19.2MHz, 25MHz
and 50MHz, the default frequency is 50MHz.
The SPI0 interface can be configured as UART (UART4) interface by means of open CPU API or AT command
(see the TOBY-L3 series AT Commands Manual [2]), for communication with external devices with the
following configuration Table 13:
SPI Mode (SPI0)
4-wire UART Mode (UART4)
SPI_MOSI; SPI0 MOSI Pin (Module Output)
RXD4 (Module output); UART4 Receive Data
SPI_MISO; SPI0 MISO Pin (Module Input)
TXD4 (Module Input); UART4 Transmit Data
SPI_SCLK; SPI0 Clock Pin (Module Output)
CTS4 (Module Output); UART4 Clear To Send
SPI_CS; SPI0 Chip Select Pin (Module Output)
RTS4 (Module Input); UART4 Ready To Send
Table 14: TOBY-L3 series modules SPI0 PINs configuration
1.9.4 DDC (I2C) interfaces
1.9.4.1 I2C0 interface
The SDA and SCL pins represent the I2C0 1.8 V I
2
C bus compatible Display Data Channel (DDC) interface,
with the module acting as I
2
C master, available for
communication with u-blox GNSS chips / modules
communication with other external I
2
C devices by means of the open CPU API or AT commands
I2C0 interface pins of the module are open drain outputs conforming to the I
2
C bus specifications [7],
supporting up to 100 kbit/s data rate in Standard-mode, and up to 400 kbit/s data rate in Fast-mode.
Tashang has implemented special features to ease the design effort required for the integration of the
TOBY-L3 cellular module with a u-blox GNSS device.
Combining the TOBY-L3 cellular module with a u-blox GNSS device allows designers to have full access to
the positioning device directly via the cellular module: it relays control messages to the GNSS device via a