Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 48 of 143
The UART1 interface can be alternatively, in mutually exclusive way, configured as SPI (SPI2), I2S (I2S1) or
PCM (PCM1) interface by means of open CPU API or AT command (see the TOBY-L3 series AT Commands
Manual [2]), for communication with external devices with the following configuration Table 13:
4-wire UART Mode (UART1)
SPI Mode (SPI2)
I2S Mode (I2S1)
PCM Mode (PCM1)
RXD1 (Module output);
UART1 Receive Data
SPI2_MOSI;
SPI2 MOSI Pin (Module Output)
I2S1_WA;
I2S1 Word alignment
PCM1_SYNC;
PCM1 Frame Sync
TXD1 (Module Input);
UART1 Transmit Data
SPI2_MISO;
SPI2 MISO Pin (Module Input)
I2S1_RXD;
I2S1 Receive Data In
PCM1_DIN;
PCM1 Data In
CTS1 (Module Output);
UART1 Clear To Send
SPI2_CLK;
SPI2 Clock Pin (Module Output)
I2S1_CLK;
I2S Serial Clock
PCM1_CLK;
PCM1 Clock
RTS1 (Module Input);
UART1 Ready To Send
SPI2_CS;
SPI2 Chip Select Pin (Module Output)
I2S1_TXD;
I2S1 Transmit Data Out
PCM1_DOUT;
PCM1 Data Out
Table 13: TOBY-L3 series modules UART1 PINs configuration
1.9.2.3 UART2 interface
☞ The UART2 interface is used for LTE-ISM concurrency only.
The UART2 two wire Universal Asynchronous Receiver/Transmitter serial interface (TXD2 and RXD2 pin) is
only used for the LTE and ISM concurrency procedure. The UART2 has CMOS compatible signal levels
(0 V for ON / active state and 1.8 V for OFF / idle state). As some LTE band and Wi-Fi band or BT band is
overlapped, to avoid the RF interference, the module provide the UART2 interface to exchange the wireless
information message and the control commands.
The UART2 interface is only used for LTE-ISM concurrency, over the following pins:
RXD2 module output and TXD2 module input data lines
UART2 interface can operate at 300bit/s, 600bit/s, 1.2kbit/s, 2.4kbit/s, 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4
kbit/s, 57.6kbit/s, 115.2kbit/s, 230.4kbit/s, 1Mbit/s, 3Mbit/s, 4Mbit/s baud rates, with 8N1 frame format.
1.9.2.4 UART3 interface
The UART3 Universal Asynchronous Receiver/Transmitter serial interface has CMOS compatible signal levels
(0 V for ON / active state and 1.8 V for OFF / idle state), providing:
Linux console for open CPU API development and debug, over the following pins:
o RXD3 module output and TXD3 module input data lines
UART3 interface can operate at 300bit/s, 600bit/s, 1.2kbit/s, 2.4kbit/s, 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4
kbit/s, 57.6kbit/s, 115.2kbit/s, 230.4kbit/s, 1Mbit/s, 3Mbit/s, 4Mbit/s baud rates, with 8N1 frame format.