Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 43 of 143
UART interfaces (see section 1.9.2):
o UART0 interface, providing:
Can be configured as SPI (SPI1) interface by open CPU API or AT commands alternatively.
Communication with external serial devices by means of open CPU API or AT commands.
o UART1 interface, providing:
Can be configured as I2S (I2S1), PCM (PCM1) or SPI (SPI2) interface by open CPU API or AT
commands alternatively.
Communication with external serial devices by means of open CPU API or AT commands.
Communication with external slave SPI devices when configured as SPI1 by means of open CPU
API
PPP data connection and AT command function.
o UART2 interface, providing:
Only used to communicate with external WI-FI/Bluetooth devices to avoid RF interference between
LTE and Wi-Fi/Bluetooth
o UART3 interface, providing:
Communication with external serial devices by means of open CPU API
Trace log capture (diagnostic purposes)
SPI interfaces
5
(see section 1.9.3):
o Can be configured as UART (UART4) interface by open CPU API or AT commands.
o SPI0 interface, with the module acting as SPI master, providing:
Communication with external SPI slave devices by means of open CPU API
Two DDC I
2
C bus compatible interfaces (see section 1.9.4):
o I2C0 interface, with the module acting as I
2
C master, providing:
Communication with u-blox GNSS positioning chips / modules
Communication with external I
2
C slave devices by means of open CPU API
o I2C1 interface, with the module acting as I
2
C master, providing:
Communication with external I
2
C slave devices by means of open CPU API
SDIO interface
5
, with the module acting as SDIO host, providing (see section 1.9.5):
Communication with compatible u-blox short range radio modules by means of open CPU API
Communication with external SDIO devices by means of open CPU API
SGMII interface, with the module acting as Ethernet MAC, providing (see section 1.9.6):
Ethernet connection enabled through the external compatible Ethernet PHY SIM interfaces
1.9.1 USB interface
TOBY-L3 series modules include a USB High-Speed 2.0 interface, supporting up to 480 Mbit/s data rate.
5
Not supported by "0x" product feature version