Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 34 of 143
Figure 13 shows the module power-on sequence, describing the following phases:
The VCC module supply is stable at its nominal value within the normal operating range
The PWR_ON input pin is set low for a valid time period, representing the switch-on event.
All the generic digital pins of the modules are tri-stated until the switch-on of their supply source (V_INT):
any external signal connected to the generic digital pins must be tri-stated or set low at least until the
activation of the V_INT supply output to avoid latch-up of circuits and allow a clean boot of the module.
The V_INT generic digital interfaces supply output is enabled by the integrated power management unit.
The RESET_N line rises suddenly to the high logic level due to internal pull-up to V_INT.
The internal reset signal is held low by the integrated power management unit: the baseband processor
core and all the digital pins of the modules are held in reset state.
When the internal reset signal is released, any digital pin is set in the correct sequence from the reset
state to the default operational configured state. The duration of this pins’ configuration phase differs
within the generic digital interfaces and the USB interface due to host / device enumeration timings (see
section 1.9.1).
The module sends the “+AT: READY” URC notification over the AT communication interface (USB) when
it is ready to receive AT commands
The module is fully ready to operate after all interfaces are configured.
VCC
PWR_ON
V_INT
RESET_N
Internal Reset
System State
Digital Pins State
Internal Reset
→
Operational Operational
Tristate / Floating
OFF
ON
Internal Reset
0 ms
~35 ms
~3 s
Start of interface
configuration
Module interfaces
are configured
The module starts
the switch-on routine
Figure 13: TOBY-L3 series power-on sequence description
☞ The Internal Reset signal is not available on a module pin, but it is recommended to monitor:
o the V_INT pin, to sense the start of the module switch-on sequence
o the “+AT: READY” URC notification, to sense when the module is ready to operate
☞ Before the switch-on of the generic digital interface supply (V_INT) of the module, no voltage driven
by an external application should be applied to any generic digital interface of the module.
☞ Before the TOBY-L3 series module is fully ready to operate, the host application processor should not
send any AT command over the AT communication interface (USB) of the module.