Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 20 of 143
Function
Pin Name
Pin No
I/O
Description
Remarks
I2S_RXD
53
I /
I
I2S0 receive data /
PCM0 data in
I
2
S (I2S0) receive data input.
Alternatively configurable as PCM0 data in by Open CPU or
AT Command.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S_CLK
52
I/O
/
I/O
I2S0 clock /
PCM0 clock
I
2
S (I2S0) serial clock.
Alternatively configurable as PCM0 clock by Open CPU or AT
Command.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
I2S_WA
50
I/O
/
I/O
I2S0 word alignment /
PCM0 frame sync
I
2
S (I2S0) word alignment.
Alternatively configurable as PCM0 frame sync by Open CPU
or AT Command.
See sections 1.11 for functional description.
See sections 2.8 for external circuit design-in.
ADC
ADC1
240
I
ADC input
See section 1.12 for functional description.
See section 2.9 for external circuit design-in.
ADC2
239
I
ADC input
See section 1.12 for functional description.
See section 2.9 for external circuit design-in.
GPIO
GPIO1
21
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO2
22
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO3
24
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
Configurable as External Interrupt by open CPU API.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO4
25
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
Configurable as SPI0 Chip Select 1 by open CPU API.
See sections 1.13, 1.9.2.3 for functional description.
See sections 2.10, 2.6.3 for external circuit design-in.
GPIO5
60
I/O
GPIO
Used as the SIM card detection by default.
Alternately settable as normal GPIO by open CPU API or
AT commands.
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.
GPIO6
61
I/O
GPIO
1.8 V GPIO with alternatively configurable functions.
See section 1.13 for functional description.
See section 2.10 for external circuit design-in.