Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 122 of 143
Do not apply loads which might exceed the limit for the maximum available current from V_INT
supply.
Check that the voltage level of any connected pin does not exceed the relative operating range.
Provide accessible test points directly connected to the following pins of the TOBY-L3 series modules:
V_INT, PWR_ON and RESET_N for diagnostic purposes.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if
accessible.
Check UART signals direction, as the modules’ signal names follow the ITU-T V.24 Recommendation
[6].
Provide accessible test points directly connected to all the UART pins of the TOBY-L3 series modules
(TXD, RXD) for diagnostic purposes.
Provide accessible test points directly connected to all the UART3 pins of the TOBY-L3 series
modules (TXD3, RXD3) for Linux debug console access.
Capacitance and series resistance must be limited on each high speed line of the USB interface.
Provide accessible test points directly connected to the USB 2.0 interface pins of the TOBY-L3 series
modules (VUSB_DET, USB_D+ and USB_D–) for diagnostic and FW update purposes.
Consider providing appropriate low value series damping resistors on SDIO lines to avoid reflections.
Add a suitable pull-up resistor (e.g. 4.7 k) to V_INT or another suitable 1.8 V supply on each DDC
(I
2
C) interface line, if the interface is used.
Check the digital audio interface specifications to connect a suitable external audio device.
Capacitance and series resistance must be limited on master clock output line and each I
2
S interface
line
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor
on the board in series to the GPIO when those are used to drive LEDs.
Provide suitable precautions for EMC / ESD immunity as required on the application board.
Do not apply voltage to any generic digital interface pin of TOBY-L3 series modules before the
switch-on of the generic digital interface supply source (V_INT).
All unused pins of TOBY-L3 series modules can be left unconnected, which must all be connected
to GND.
2.15.2 Layout checklist
The following are the most important points for a simple layout check: