Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 117 of 143
☞ The ESD sensitivity rating of ADC pins is 1 kV (HBM according to JESD22-A114). Higher protection level
could be required if the lines are externally accessible and it can be achieved by mounting an ESD
protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points.
☞ If the ADC pins are not used, they can be left unconnected on the application board.
2.9.2 Guidelines for ADC layout design
The Analog to Digital Converters (ADC1, ADC2) are high impedance analog inputs. The conversion accuracy
will be degraded if noise is injected. Low-pass filter may be used to improve noise rejection; typically, L-C
tuned for RF rejection gives better results.
2.10 General Purpose Input/Output
2.10.1 Guidelines for GPIO circuit design
A typical usage of TOBY-L3 series modules’ GPIOs can be the following:
Wi-Fi enable function provided by GPIO6 (see Figure 55 in section 2.6.5)
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GNSS supply enable function provided by GPIO2 (see Figure 51, Figure 53 in section 2.6.4)
12
GNSS Tx data ready function provided by GPIO3 (see Figure 51, Figure 53 in section 2.6.4)
12
SIM card detection provided by the GPIO5 (see Figure 38 / Table 32 in section 2.5)
Other configurations of the TOBY-L3 series modules’ GPIOs are possible, as shown in section 1.13.
☞ Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on
the board in series with the GPIO of TOBY-L3 series modules.
☞ Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (V_INT), to
avoid latch-up of circuits and allow a clean module boot. If the external signals connected to the module
cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159,
TS5A63157) between the two-circuit connections and set to high impedance before V_INT switch-on.
☞ The ESD sensitivity rating of the GPIO pins is 1 kV (HBM according to JESD22-A114). Higher protection
level could be required if the lines are externally accessible and it can be achieved by mounting an ESD
protection (e.g. EPCOS CA05P4S14THSG ) close to the accessible points.
☞ If the GPIO pins are not used, they can be left unconnected on the application board.
12
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