Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 102 of 143
Figure 49 describes a possible application circuit for the SPI0 interface, where two SPI slave devices are
connected to the module using the two SPI0 Chip Select 0 (SPI_CS pin) to select the specific SPI slave
device.
The external SPI slave device must provide compatible voltage levels (1.80 V typ.), otherwise it is
recommended to connect the 1.8 V SPI interface of the module to the external 3.0 V (or similar) SPI device
by means of appropriate unidirectional voltage translators (e.g. TI SN74AVC4T774 or SN74AVC2T245,
providing partial power down feature so that the digital audio device 3.0 V supply can be also ramped up
before V_INT 1.8 V supply), using the module’s V_INT output as a 1.8 V supply for the voltage translators
on the module side.
TOBY-L3 series
(Master, 1.8V)
SCLK
CS
MOSI
MISO
GND
SPI_SCLK
SPI_CS
SPI_MOSI
SPI_MISO
SPI Device
(Slave, 1.8V)
GND
Figure 49: SPI interface application circuit for connecting external SPI slave devices
☞ Do not apply voltage to any SPI interface pins before the switch-on of the SPI supply source (V_INT),
to avoid latch-up of circuits and allow a clean boot of the module.
☞ The ESD sensitivity rating of SPI pins is 1 kV (HBM according to JESD22-A114). A higher protection level
could be required if the lines are externally accessible and it can be achieved by mounting an ESD
protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points.
☞ If the SPI interfaces pins are not used, they can be left unconnected on the application board.
2.6.3.2 Guidelines for SPI layout design
The SPI serial interface requires the same considerations regarding electro-magnetic interference as any
other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs,
since the signals can cause the radiation of some harmonics of the digital data frequency.
2.6.4 DDC (I2C) interfaces
2.6.4.1 General guidelines for DDC (I2C) circuit design
The DDC I
2
C-bus pins of the module are open drain outputs conforming to I
2
C bus specifications [7].
External pull-up resistors to a suitable 1.8 V supply (e.g. V_INT) are required for operations: for example,
4.7 k resistors can be commonly used.