Integration Manual
Table Of Contents
- Contents
- 1 System description
- 1.1 Overview
- 1.2 Architecture
- 1.3 Pin-out
- 1.4 Operating modes
- 1.5 Supply interfaces
- 1.5.1 Module supply input (VCC)
- 1.5.1.1 VCC supply requirements
- 1.5.1.2 VCC current consumption in 2G connected mode
- 1.5.1.3 VCC current consumption in 3G connected mode
- 1.5.1.4 VCC current consumption in LTE connected mode
- 1.5.1.5 VCC current consumption in cyclic low power idle mode / active mode
- 1.5.1.6 VCC current consumption in fixed active mode
- 1.5.2 Generic digital interfaces supply output (V_INT)
- 1.5.1 Module supply input (VCC)
- 1.6 System function interfaces
- 1.7 Antenna interfaces
- 1.8 SIM interfaces
- 1.9 Data communication interfaces
- 1.10 eMMC interface
- 1.11 Digital Audio interfaces
- 1.12 ADC interfaces
- 1.13 General Purpose Input/Output
- 1.14 Reserved pins (RSVD)
- 1.15 System features
- 1.15.1 Network indication
- 1.15.2 Jamming detection
- 1.15.3 IP modes of operation
- 1.15.4 Dual stack IPv4 and IPv6
- 1.15.5 Embedded TCP/IP and UDP/IP
- 1.15.6 Embedded FTP and FTPS
- 1.15.7 Embedded HTTP and HTTPS
- 1.15.8 SSL and TLS
- 1.15.9 Firmware update Over AT (FOAT)
- 1.15.10 Firmware update Over The Air (FOTA)
- 1.15.11 Power Saving
- 2 Design-in
- 2.1 Overview
- 2.2 Supply interfaces
- 2.2.1 Module supply (VCC)
- 2.2.1.1 General guidelines for VCC supply circuit selection and design
- 2.2.1.2 Guidelines for VCC supply circuit design using a switching regulator
- 2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator
- 2.2.1.4 Guidelines for VCC supply circuit design using a rechargeable battery
- 2.2.1.5 Guidelines for VCC supply circuit design using a primary battery
- 2.2.1.6 Additional guidelines for VCC supply circuit design
- 2.2.1.7 Guidelines for the external battery charging circuit
- 2.2.1.8 Guidelines for external charging and power path management circuit
- 2.2.1.9 Guidelines for removing VCC supply
- 2.2.1.10 Guidelines for VCC supply layout design
- 2.2.1.11 Guidelines for grounding layout design
- 2.2.2 Generic digital interfaces supply output (V_INT)
- 2.2.1 Module supply (VCC)
- 2.3 System functions interfaces
- 2.4 Antenna interface
- 2.5 SIM interfaces
- 2.6 Data communication interfaces
- 2.7 eMMC interface
- 2.8 Digital Audio interface
- 2.9 ADC interfaces
- 2.10 General Purpose Input/Output
- 2.11 Reserved pins (RSVD)
- 2.12 Module placement
- 2.13 Module footprint and paste mask
- 2.14 Thermal guidelines
- 2.15 Design-in checklist
- 3 Handling and soldering
- 4 Approvals
- 5 Product testing
- 6 FCC Notes
- Appendix
- Glossary
- Related documents
- Revision history
- Contact
TOBY-L3 series - System Integration Manual
TSD-19090601 - R13 System Integration Manual Page 101 of 143
5
V_INT
RI
3V Processor / Device
GND
TOBY-L3 series
11
RI
GND
1V8
B1 A1
GND
U1
VCCB
VCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR2
OE
VCC
B2 A2
TP
DIR1
Figure 48: Ring Indicator(Configured by GPIO8) application circuit to connect an external 3.0V processor / device
Reference
Description
Part Number - Manufacturer
C1, C2
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional Voltage Translator
SN74AVC2T245
9
- Texas Instruments
Table 37: Component for the Ring Indicator application circuit to connect an external 3.0V processor / device
☞ Do not apply voltage to any UART interfaces pin before the switch-on of the UART supply source
(V_INT), to avoid latch-up of circuits and allow a clean boot of the module.
☞ The ESD sensitivity rating of UART pins is 1 kV (HBM according to JESD22-A114). A higher protection
level could be required if the lines are externally accessible and it can be achieved by mounting an ESD
protection (e.g. EPCOS CA05P4S14THSG) close to the accessible points.
☞ If the UART interfaces pins are not used, they can be left unconnected on the application board, but it
is recommended to provide accessible test points directly connected to the UART0 TXD and RXD pins
for diagnostic purposes.
2.6.2.2 Guidelines for UART layout design
The UART serial interface requires the same considerations regarding electro-magnetic interference as any
other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs,
since the signals can cause the radiation of some harmonics of the digital data frequency.
2.6.3 SPI interfaces
☞ SPI interfaces are not supported by the "0x" product feature versions.
2.6.3.1 Guidelines for SPI circuit design
TOBY-L3 series modules include up to two 1.8 V Serial Peripheral Interfaces to communicate with external
SPI slave devices, with the module acting as SPI master, by means of the open CPU API.
9
Voltage translator providing partial power down feature: the external 3.0 V supply can be ramped up before V_INT 1.8 V supply