Datasheet

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D
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The takeMS 184pin DDR SDRAM DIMM series is unbuffered 184-pin double data rate Synchronous DRAM Dual
In-Line Memory Modules which are organized as 32/64Mx64 high-speed memory arrays. The modules (Single Side
or Double Side) consists of eight or sixteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-
epoxy substrate. It is suitable for easy interchange and addition.
The takeMS 184pin DDR SDRAM DIMM series is designed for high speed of up to 200MHz and offers fully
synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses
and control inputs are latched on the rising edges of the clock, Data(DQ), Data strobes(DQS) and Write data masks
inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit
prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High
speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance
memory system.
The takeMS 184pin DDR SDRAM DIMM series incorporates SPD (serial presence detect).
Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data
are programmed by takeMS to identify DIMM type, capacity and other information of DIMM.
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* 256/512MB Unbuffered DDR DIMM based on * Data(DQ), Data strobes & Write masks latched
32Mx8 DDR SDRAM on both rising & falling edges of the clock
* JEDEC Standard 184pin dual in-line memory module(DIMM) * 2.6V +/- 0.2V VDD & VDDQ Power supply
* Data inputs on DQS centers when write (centered DQ) * Programmable CAS Latency 2 /2.5 supported
* Data strobes synchronized with output data for read & input * Internal four bank operations with single pulsed
data for write RAS
* All inputs & outputs are compatible with SSTL_2 interface * Auto refresh& self refresh supported
* Fully differential clock operations (CLK & CLK) with * Programmable Burst Length 2/4/8 with both
200MHz sequential 7 interleave mode
* All addresses & control inputs except Data, Data strobes & * 4096 refresh cycles / 64ms
Data masks latched on the rising edges of the clock
Clock
Frequency
Interface Power
Supply
SDRAM
Package
200MHz (PC3200)
DDR 400 CL2.5=200
DDR 333 CL2.5=166
DDR 266 CL2=133
SSTL_2 VDD=2.6V
VDDQ=2.6V
400mil 66pin
TSOP II
Jul 2005
This document is a general product description and is subject to change without notice. takeMS does not assume any responsibility for use of
circuits described. No patent licenses are implied. takems is a trademark of Memorysolution GmbH