Datasheet

TSM950N10CW
Taiwan Semiconductor
2 Version: D1807
ELECTRICAL SPECIFICATIONS (T
A
= 25°C unless otherwise noted)
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
Static
(Note 3)
Drain-Source Breakdown Voltage
V
GS
= 0V, I
D
= 250µA
BV
DSS
100
--
--
V
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250µA
V
GS(TH)
1.2
1.6
2.5
V
Gate Body Leakage
V
GS
= ±20V, V
DS
= 0V
I
GSS
--
--
±100
nA
Zero Gate Voltage Drain Current
V
DS
= 100V, V
GS
= 0V
I
DSS
--
--
1
µA
Drain-Source On-State Resistance
V
GS
= 10V, I
D
= 5A
R
DS(on)
--
80
95
mΩ
V
GS
= 4.5V, I
D
= 3A
--
85
110
Dynamic
(Note 4)
Total Gate Charge
V
DS
= 48V, I
D
= 5A,
V
GS
= 10V
Q
g
--
9.3
--
nC
Gate-Source Charge
Q
gs
--
2.1
--
Gate-Drain Charge
Q
gd
--
1.8
--
Input Capacitance
V
DS
= 50V, V
GS
= 0V,
f = 1.0MHz
C
iss
--
1480
--
pF
Output Capacitance
C
oss
--
480
--
Reverse Transfer Capacitance
C
rss
--
35
--
Gate Resistance
f = 1MHz, open drain
R
g
--
1.3
--
Ω
Switching
(Note 5)
Turn-On Delay Time
V
DD
= 30V,
R
GEN
= 3.3Ω,
I
D
= 1A, V
GS
= 10V,
t
d(on)
--
2.9
--
ns
Turn-On Rise Time
t
r
--
9.5
--
Turn-Off Delay Time
t
d(off)
--
18.4
--
Turn-Off Fall Time
t
f
--
5.3
--
Source-Drain Diode
(Note 3)
Forward On Voltage
I
S
= 3.3A, V
GS
= 0V
V
SD
--
--
1
V
Continuous Drain-Source Diode
I
S
--
--
6.5
A
Pulse Drain-Source Diode
I
SM
--
--
26
A
Notes:
1. Current limited by package
2. Pulse width limited by the maximum junction temperature
3. Pulse test: PW ≤ 300µs, duty cycle ≤ 2%
4. For DESIGN AID ONLY, not subject to production testing.
5. Switching time is essentially independent of operating temperature.