Technical Manual

10-6
Chart 4. Bootstrap Fail
Note: This
configuration
indicates the
µC is in
Bootstrap
mode waiting
for data.
Host µC
Bootstrap Failure.
Synopsis
The host µC bootstrap mode is
used during reprogramming of
the host µC and DSP FLASH
ROMs. Refer to appropriate
Theory of operation section for
description of bootstrap
operation. Since the operating
code is downloaded through the
serial bus instead of from the
ROM and is initially executed in
the µC internal RAM, this is a
good method of verifying
operation of the µC. Basic
failure modes:
1) Necessary supplies,
grounds, system clocks not
present.
2) Vpp voltage not set to
correct voltage for bootstrap
mode select or FLASH
programming.
3) Improper configuration of
mode select pins.
4) Improper operation of RESET
to the host µC.
5) Improper
configuration/operation of the
host µC serial bus.
Verify standard
bias per table
Table 3.
No
Isolate and
repair problem.
See Chart C.5.
Yes
Standard
bias OK?
Verify voltage at VR119
(OPTB+/BOOT_SEL/VPP)
is: 10VDC≤VPP≤12.7VDC.
VPP is
correct?
Isolate open
and repair or
adjust VPP as
required.
No
Yes
Verify MODA and MODB of
U701 are pulled to a logic
low state (< .8VDC).
MODA and
MODB are
correct?
Repair inverter
circuit consisting
of VR119 and
Q104.
No
With the host µC out of
reset and prior to any
downloading through the
serial bus:
Verify U701-PD1
(BOOT_DATA_OUT) is logic
low and U701 -PD0 is logic
high (BOOT_DATA_IN).
Yes
PD0 and PD1
are correct?
Verify
BOOT_DATA_IN and
BOOT_DATA_OUT
are isolated by
MUX U704.
1
2
Yes
No
In some
circumstances
additional code is
downloaded and
placed in external
RAM. In this
case, a failure of
the external RAM
could look like a
boostrap failure.
1
2
Initiate download
and verify the
data on
BOOT_DATA_IN is
echoed out on
BOOT_DATA_OUT
.
Signals are
isolated?
Verify MUX
control on Pin
4 of U704 is
low.
Yes
No
Control
voltage
correct?
Verify continuity
between U704-4,
R167, Q104, and
U701 and repair any
open signal traces.
Replace U704.
Yes
No
Data echoed?
Replace U701.
MAEPF-26017-O
Yes
No
Verify continuity
of BOOT_DATA_IN
from J101-6 to
U701-PD0.
Signal good?
Yes
Verify U701 ECLK
is 1.8432 MHZ
±200ppM.
Replace Y100.
Verify download
baud rate is 7200.
Baud rate
correct?
ECLK frequency
correct?
Isolate and
repair open.
No
Fix baud rate.
Yes
Yes
No
No