SB4002A_Data Sheet_EN

SB4002A
82
Table 8-3. Legacy Bus Timing Specifications for Read Access
BYTE_EN
IOR#
Trh
ADDRESS
Td4
DATA
CS#
Td5
Trs
MEMR#
Tr1
Figure 8-4. Legacy Bus Timing Specifications for Read Access
Symbol
Parameter
Min
Typ
Max
Units
Td5
CS#/EA/BYTE_EN# assert to
IOR#/MEMR# assert
-
1
-
PCI
CLK
Td6
IOR#/MEMR# deassrt to
CS#/EA/BYTE_EN# deassert
-
1
-
PCI
CLK
Trs
ED valid to IOR#/MEMR# disable
(required setup time for read on 66MHz)
15.5
-
-
ns
ED valid to IOR#/MEMR# disable
(required setup time for read on 33MHz)
19.5
-
-
Trh
IOR#/MEMR# disable to ED unvalid
(reguired hold time for read)
0
-
-
PCI
CLK
Tr1
IOR#/MEMR# width
-
n
-
PCI
CLK
* ‘n’ meams IOR#/MEMR# signal width is ‘n’ times PCI CLK.
‘n’ would be determined by Base Address Space Setting Register[10:8], Refer to Chapter 6