SB4002A_Data Sheet_EN

SB4002A
79
8. Timing Specification
8.1 PCI BUS Timing Specifications
66MHz
33MHz
Symbol
Parameter
Min
Max
Min
Max
Units
Tval
CLK to Signal Valid Delay -
Bused Signals
2
6
2
11
ns
Tval(ptop)
CLK to Signal Valid Delay -
point to point Signals
2
6
2
12
ns
Ton
Float to Active Delay
2
2
ns
Toff
Active to Float Delay
14
28
ns
Tsu
Input Setup Time to CLK -
bused Signals
3
7
ns
Tsu(ptop)
Input Setup Time to CLK -
point to point signals
5
10,12
ns
Th
Input Hold Time from CLK
0
0
ns
Trst
Reset Active Time after power stable
1
1
ms
Trst-clk
Reset Active Time after CLK stable
100
100
us
Trst-off
Reset Active to output float delay
40
40
ns
Trhfa
RST# high to first Configuration access
2 25
2 25
clocks
Trhff
RST# high to first FRAME# assertion
5
5
clocks
Table 8-1. PCI Bus Timing Specifications