SB4002A_Data Sheet_EN

SB4002A
72
7.2 Pin Description
Signal
Name
Pin
No.
Pin
Type
Description
PCI Bus Signal
CLK
33
in
PCI
Provides timing for all actions of PCI bus. The signal gives input for all
the PCI devices, and its rising edge becomes the reference for
input/output and timing constant of all signals. (exception: RST#,
INTx#, PME#, CLKRUN# )
PRST#
32
in
PCI
Reset signal of the PCI system.
AD[31:0]
-
t/s
Address/Data multiplexed signal. This signal is used during the PCI
transaction as the address signal in the address phase or as the data
signal in the data phrase.
( Pin No. : 35, 37, 38, 39, 40, 41, 42, 43, 46, 48, 49, 50, 51, 52, 55, 56,
69, 70, 71, 74, 75, 76, 77, 78, 80, 81, 82, 83, 84, 85, 86, 87 )
C/BE[3:0]#
-
t/s
Bus Command/Byte Enable multiplexed signal. It is used during the
PCI transaction as BUS Command in the address phase or as Byte
Enable in the data phrase.
( Pin No. : 44, 57, 67, 79 )
PAR
68
t/s
Provides the even parity for AD[31:0] and C/BE[3:0].
FRAME#
58
s/t/s
Indicates start and continuance of PCI transaction.
IRDY#
59
s/t/s
Initiator Ready. The signal indicates that the BUS master is ready to
output data.
TRDY#
60
s/t/s
Target Ready. The signal indicates that the target device is ready to
output data.
STOP#
64
s/t/s
Used by the target to request the master to stop PCI transaction.
LOCK#
65
s/t/s
Used for exclusive access.
IDSEL
45
in
Indicates that a device is selected for configuration access.
DEVSEL#
61
s/t/s
Device Select. Used by the selected target to indicate that it is
selected.
PERR#
66
s/t/s
Parity Error. Indicates that a parity error occurs in the data phase.