SB4002A_Data Sheet_EN

SB4002A
68
Poll Register
POL4Reserved
2 1
POL0
4 03
POL1POL2
7
POL3
5
Table 6-9. Poll Register Layout
Indicates the interrupt status on the Legacy bus regardless of the enable register value.
Bit[4] : POL4, 1 : Indicates generation of an INT5.
Bit[3] : POL3, 1 : Indicates generation of an INT4.
Bit[2] : POL2, 1 : Indicates generation of an INT3.
Bit[1] : POL1, 1 : Indicates generation of an INT2.
Bit[0] : POL0, 1 : Indicates generation of an INT1.
Endian & LOCK Control Register
Endian Select
07
Reserved
LOCK# Enable
1
Table 6-10. Endian & LOCK Control Register Layout
Sets the values for other supplementary functions.
Bit[1] : Endian Select (R/W)
Big Endian for 1b and Little Endian for 0b, Default:0b
Bit[0] - LOCK# Enable : If this bit is 1b, the exclusive access is started in response to LOCK#, Default:0b