SB4002A_Data Sheet_EN

SB4002A
67
Interrupt Enable Register
4
Reserved IE2
35 0
IE4
2
IE0
1
IE1IE3
7
Table 6-7. Interrupt Enable Register Layout
Enables/Disables 5 interrupt signals. (R/W)
Bit[4] : IE4, 1b : Enables INT5, 0b : Disables INT5(Default).
Bit[3] : IE3, 1b : Enables INT4, 0b : Disables INT4(Default).
Bit[2] : IE2, 1b : Enables INT3, 0b : Disables INT3(Default).
Bit[1] : IE1, 1b : Enables INT2, 0b : Disables INT2(Default).
Bit[0] : IE0, 1b : Enables INT1, 0b : Disables INT1(Default).
Interrupt Polarity Register
IP3 IP2
7
Reserved
15 02
IP4
34
IP0IP1
Table 6-8. Interrupt Polarity Register Layout
Indicates polarities of 5 interrupt signals.(R/W)
Bit[4] : IP4, 1b : INT5 is positive polarity, 0b : INT5 is negative polarity(Default).
Bit[3] : IP3, 1b : INT4 is positive polarity, 0b : INT4 is negative polarity(Default).
Bit[2] : IP2, 1b : INT3 is positive polarity, 0b : INT3 is negative polarity(Default).
Bit[1] : IP1, 1b : INT2 is positive polarity, 0b : INT2 is negative polarity(Default).
Bit[0] : IP0, 1b : INT1 is positive polarity, 0b : INT1 is negative polarity(Default).