SB4002A_Data Sheet_EN

SB4002A

If a new read cycle is started after retry, the previous cycle is disregarded. If a PCI cycle is

started when a read cycle on the Legacy bus is not finished, the device ends the cycle with

retry.

5. Delayed Time Read with Prefetch

It is applied to a burst transfer only. On receiving the initial access, the device stores the

address and command, finishes the PCI bus cycle with retry, and after an appropriate time

period, executes a read transaction on the Legacy bus. The length of IOR# is bit[12:10]+001b,

and the time between deassertion of an IOR# and assertion of the next IOR# is bit[18:16]

+010b. If the same cycle is started on the PCI bus, the device responds to the cycle in no wait.

The size of data prefetched at a time is designated in the bit[6:5].

If the same cycle is started when prefetched data is in FIFO, the device responds to the burst

cycle for the prefetched data. If the cycle is requested continuously, the device terminates the

transaction with disconnect. The Legacy bus keeps executing the prefetch.

If a new read cycle or a write cycle is started for other address when prefetch is not finished on

the Legacy bus, the device terminates the transaction with retry.

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※ CS# is PCI 1 CLK length added before and after IOW# and IOR#.

※ The wait cycle must follow the 8 CLK rule. In other words, after TRDY# is deasserted in the

burst transfer, TRDY# must be asserted within 8 PCI CLK.

※ In the 8-bit data space mode, if a 16-bit access is started on the PCI bus, two 8-bit

accesses must be executed. If a 32-bit access is executed, four 8-bit accesses must be

executed.

If a 32-bit access is started on the PCI bus in the 16-bit data path, two 16-bit accesses must

be executed.

※ Errata : A real time read burst is executed on the assumption that byte enable is not

changed during the access. If the byte enable is changed during the access, an erroneous

value can be read. Therefore, if byte enable is changed during the access, it is recommended

to use the delayed time mode instead of the real time mode.