SB4002A_Data Sheet_EN

SB4002A

Bit[10:8] : WR# Adding Length for Legacy Bus (R/W)

Basically, IOW# has the enable length of PCI 1 CLK.

The length is extended by the value set in this value.

This bit is used to control the wait cycle on the PCI bus in the real time write.

Bit[6:5] : READ Prefetch Byte (R/W)

Supported in the delay time read mode only.

00b – Prefetch by 2-DWORD (Default)

01b – Prefetch by 4-DWORD

10b - Prefetch by 8-DWORD

11b - Prefetch by 16-DWORD

Bit[4] : READ Prefetch Enbale (R/W)

1b enables READ prefetch, and 0b disables READ prefetch. The default is 0b.

Bit[3:2] : READ Mode for PCI Bus (R/W)

00 b- Real time read / Burst not supported (Default/FIFO not used)

01b - Real time read / Burst supported (FIFO not used)

10b - Delayed time read (retry used) / Burst not supported (FIFO 1 byte used)

11b - Delayed time read (retry used) / Burst supported (FIFO n byte used / prefetch enable)

Bit[1:0] : WRITE Mode for PCI Bus (R/W)

00 - Real time write / Burst not supported (Default/FIFO not used)

01 - Real time write / Burst supported (FIFO not used)

10 - Delayed time write / Burst not supported (FIFO 1 byte used)

11 - Delayed time write / Burst supported (FIFO n byte used)

Tips : PCI Bus and Legacy Bus Description

1. Real Time Write

In a single transfer, when DEVSEL# is asserted, TRDY# is asserted at the same time to catch

the data, and CS# is also asserted to output the address. Then, the device deasserts

DEVSEL# and TRDY# to end the PCI cycle, asserts IOW# on the Legacy bus, and outputs the

data. The device maintains IOW# for the bit[9:7]+01b before deasserting it, deasserts CS# at

the next CLK, and then removes the address and data. In a burst transfer, when DEVSEL# is

asserted, TRDY# is asserted at the same time to catch the data, and CS# is also asserted to

output the address. Then, the device deasserts TRDY#, asserts IOW# on the Legacy bus, and

outputs the data. The device, then, maintains IOW# for the bit[9:7]+01b before deasserting it.

The device asserts TRDY# after the next bit[15:13]+01b, and sends the address on the