SB4002A_Data Sheet_EN

SB4002A

5. Miscellaneous Feature

5.1 Interrupt

In order to enable the PCI interrupt service, SB4002A provides 5 interrupt pins to the Legacy bus.

In general, the I/O devices use the interrupt and provide total 5 base addresses, SB4002A provides

5 interrupt pin sources. However, the interrupt pins can be used regardless of the address. For

example, an I/O base address can use 2 or more interrupt pins.

Because the interrupt features vary by the devices, SB4002A provides the interrupt active level

setting register, the enable/disable register, and the poll register for each pin. These registers are

located in the internal control register. The following figure shows the interrupt block diagram.

INT1

Interrupt Poll

INT2

INT3

INT5

Interrupt Polarity

INT4

INTA#

Interrupt Enable

Figure 5-1. Interrupt Generator Schematic