SB4002A_Data Sheet_EN

SB4002A
51
Serial ROM Address (06h) : Status Register Capabilities List Enable
The PCI spec from 2.1 provides a new register set which is a linked list called as the Capabilities
List. In order to enable the Capabilities List, the Capabilities List bit (bit 4) of the PCI Status
Register must be set to 1, and the Capabilities List pointer must be in the PCI Configuration
Space 34h. In 34h, the pointer indicates the first item of the Capabilities List.
In order to use the Capabilities List, store 10h in 06h of the serial ROM. Then 1b is stored in the
PCI Status Register bit 4 of PCI Configuration Space 06h~07h. In order not to use the
Capabilities List, store 00h. Then 0b is stored in the PCI Status Register bit 4.
Serial ROM Address(07h) : Reserved
Serial ROM Address 07h is reserved for 00h data.
Serial ROM Address(08h) : Revision ID
Serial ROM Address 08h represents Revision ID[7:0] of PCI Configuration Space 08h.
Serial ROM Address(09h) : Class Code Low Byte
Serial ROM Address 09h represents the bit array [7:0] of Class Code [23:0] of PCI Configuration
Space 09h~0Bh.
Serial ROM Address(0Ah) : Class Code Middle Byte
Serial ROM Address 0Ah represents the bit array [15:8] of Class Code [23:0] of PCI Configurati-
on Space 09h~0Bh.
Serial ROM Address(0Bh) : Class Code High Byte
Serial ROM Address 0Bh represents the bit array [23:16] of Class Code [23:0] of PCI Configurat-
ion Space 09h~0Bh.
Serial ROM Address(0Ch) : Base Address1 1st Byte
Serial ROM Address 0Ch represents the first bit array [7:0] of Base Address1[31:0] in PCI Confi-
guration Space 14h~17h.
Serial ROM Address(0Dh) : Base Address1 2nd Byte
Serial ROM Address 0Dh represents the second bit array [15:8] of Base Address1[31:0] in PCI
Configuration Space 14h~17h.