SB4002A_Data Sheet_EN

SB4002A
5
Figure of Contents
Figure 2-1. PCI BUS Basic Read Transaction ................................................................................................. 12
Figure 2-2. PCI BUS Basic Write Transaction ................................................................................................. 13
Figure 2-3. DEVSEL# timing............................................................................................................................ 13
Figure 2-4. Retry .............................................................................................................................................. 14
Figure 2-5. Disconnect With Data .................................................................................................................... 15
Figure 2-6. Disconnect Without Data ............................................................................................................... 16
Figure 2-7. Target Abort ................................................................................................................................... 16
Figure 2-8. Parity Operation (First Read, Second Write) ................................................................................ 18
Figure 2-9. Starting an Exclusive Access ........................................................................................................ 37
Figure 2-10. Continuing or Releasing Exclusive Access ................................................................................. 38
Figure 3-1. Legacy Bus Real Access ............................................................................................................... 39
Figure 3-2. Legacy Bus Delayed Write Access ............................................................................................... 40
Figure 3-3. Legacy Bus Delayed Read Access ............................................................................................... 41
Figure 3-4. Legacy Bus Real Write Burst Access ............................................................................................ 41
Figure 3-5. Legacy Bus Real Read Burst Access ........................................................................................... 42
Figure 3-6. Legacy Bus Delayed Write Burst Access ...................................................................................... 42
Figure 3-7. Legacy Bus Delayed Read Burst Access ...................................................................................... 43
Figure 3-8. Legacy Bus DWORD Delayed Write Split Access for Byte Device ............................................... 44
Figure 3-9. Legacy Bus DWORD Delayed Read Split Access for Byte Device............................................... 45
Figure 5-1. Interrupt Generator Schematic ...................................................................................................... 58
Figure 5-2. GPIO Controller Schematic ........................................................................................................... 59
Figure 7-1. SB4002A Pin Location .................................................................................................................. 71
Figure 8-1. Output Timing Measurement Conditions ....................................................................................... 80
Figure 8-2. Input Timing Measurement Conditions ......................................................................................... 80
Figure 8-3. Legacy Bus Timing Specifications for Write Access...................................................................... 81
Figure 8-4. Legacy Bus Timing Specifications for Read Access ..................................................................... 82