SB4002A_Data Sheet_EN

SB4002A

IRDY#

STOP#

IOR#

TRDY#

CS#

DEVSEL#

FRAME#

CLK

Figure 3-7. Legacy Bus Delayed Read Burst Access

Single and burst in a delayed access are depending on whether it is a write access or a read

access.

In case of a delayed write access, a burst access is executed on the PCI bus, and the data are

stored in the FIFO memory. (Maximum 16 bytes. If the access request exceeds the limit, the device

terminates the transaction with disconnect.) Then the device executes the write burst access on

the Legacy bus after the PCI bus access.

In case of a delayed read access, the device predefines the burst transfer size on the Legacy bus.

If the PCI bus access is requested, the device terminates the transaction with retry. Then, the

device executes the burst access to the designated size (maximum 16 DWORD) on the Legacy

bus, and stores the data in FIFO. This process is called as a prefetch. If the transaction is restarted

on the PCI bus, the device transmits the data from FIFO. In this case, it is impossible to know how

much data the PCI bus will request. The PCI bus may request more or less data than in the

memory. In the former case, the device may terminate the transaction with Disconnect. And in the

latter case, the data stored in FIFO become invalid. Because the data may be lost in the latter case,

the device must be prefetchable, which means that the read access must not affect the address

space.