SB4002A_Data Sheet_EN

SB4002A

3.1.2 Delayed Access

This method transmits data through the transaction on the Legacy bus after the device completes

the transaction on the PCI bus. If the timing of the device is slow or the burst size is too big, data

transfer in the real access method may seize the PCI bus for a long time, and deteriorate the

overall system efficiency.

For the write process, the device finishes the PCI bus transaction at the shortest time without wait

cycle, stores the address and data in FIFO, and starts the Legacy bus transaction. This doesn't

seem much different from the real access method, but will provide the advantage over the real

access method in burst access and data byte split.

For the read process, the device stores the address, command and byte enable in the buffer, and

terminates the transaction with retry. Then, the device starts the read transaction independently on

the Legacy bus, and stores the read data in FIFO memory. When the transaction is restarted on

the PCI bus, the device outputs the data from the FIFO memory.

CS#

DEVSEL#

IOW#

CLK

FRAME#

IRDY#

TRDY#

Figure 3-2. Legacy Bus Delayed Write Access