SB4002A_Data Sheet_EN

SB4002A
34
VPD Address Register
VPD AddressF
015
Table 2-34. VPD Address Register Layout
Bit[15] F. This bit indicates that data transfer is finished between the VPD data register and the memory. For
a read event, if 0b is written on F for the address, the device sets F when the data is prepared. The
default is 0b. [R/W : non-downloadable]
Bit[14:0] VPD Address. This bit indicates the address of VPD to be accessed by DWORD. The default is 00h.
[R/W : non-downloadable]
VPD Data Register
31 0
VPD Data
Table 2-35. VPD Data Register Layout
The Configuration Space on which the device reads the VPD Data. The default is 0000h. [R/W : non-
downloadable]
In SB4002A, the VPD data are stored in the external serial EEPROM. Because this serial EEPROM is also
used to set the Configuration Space Header at system booting, this space for the Configuration Space
Header must not be overlapped with the space for VPD data. Up to the address 30h is for the Configuration
Space Header setting, and the remaining parts can be used for VPD.