SB4002A_Data Sheet_EN

SB4002A
31
PMCSR(Power Management Control/Status Register)
812
PME_En
0
Data_Select
14
Reserved
Data_Scale
79 2 1
Power State
13
PME_Status
15
Table 2-29. PMCSR Layout
This register controls power state and PME# of a device. [non-downloadable]
Bit[15] : PME_Status. This bit is set to 1b if PME# is asserted. If this bit is 1b, the register is cleared and the
PME# is deasserted. The default is 0b. [R/WC]
Bit[14:13] : Data_Scale. This bit indicates the scale of the data register value. The default is 0b.
[RO : downloadable]
Bit[12:9] : Data_Select. This bit designates the value to be read through the data register.
Bit[8] : PME_En. PME# assertion is enabled if this bit is 1b, or disabled if it is 0b. The default is 0b. [R/W]
Bit[1:0] : Power State. This bit shows the current power state. The device is in the D0 state if this bit is 00b,
D1 if it is 01b, D2 if it is 10b, and D3 if it is 11b. Because SB4002A supports D0 and D3 only, the
values 01b and 10b do not affect the device. The default is 00b.
PMCSR_BSE (PCMSR PCI to PCI Bridge Support Extension) Register
SB4002A does not support this PCI bridge related register. The default is 00h [RO : non-downloadable]
Data Register
This register is used to read the data such as power consumption and dissipation by state. The value to be
read is designated and scaled by Data_Select. The following table shows the details. [RO : downloadable]
D2 Power Dissipated
D3 Power Dissipated
D1 Power Dissipated
Data Register
1
2 : x0.01
D3 Power Consumed
2
7
D0 Power Consumed
3
D2 Power Consumed
6
8-15
5
0
D0 Power Dissipated
Reserved
D1 Power Consumed
4
Data_Scale
3 : X0.001
Data_Select
1 : x0.1
0 : unknown
Table 2-30. Data Register