SB4002A_Data Sheet_EN

ManualsBrandsSystemBase ManualsElectronic ComponentsPCI to Local Bus Bridge Controller - 60pcs Bundle

SB4002A

Table of Contents

Table 2-1. PCI Bus Signals ................................................................................................................................ 9

Table 2-2. PCI Bus Command ........................................................................................................................... 9

Table 2-3. PCI Bus I/O Addressing Rule .......................................................................................................... 10

Table 2-4. PCI Configuration Space Addressing ............................................................................................. 10

Table 2-5. PCI Configuration Header Space.................................................................................................... 19

Table 2-6. Vendor ID Register Layout .............................................................................................................. 20

Table 2-7. Device ID Register Layout .............................................................................................................. 20

Table 2-8. Command Register Layout ............................................................................................................. 20

Table 2-9. Status Register Layout .................................................................................................................... 22

Table 2-10. Revision ID Register Layout ......................................................................................................... 23

Table 2-11. Class Code Register Layout ......................................................................................................... 23

Table 2-12. Cache Line Size Register Layout ................................................................................................. 24

Table 2-13. Latency Timer Register Layout ..................................................................................................... 24

Table 2-14. Header Type Register Layout ....................................................................................................... 24

Table 2-15. BIST Register Layout .................................................................................................................... 25

Table 2-16. Base Address Register for Memory space ................................................................................... 25

Table 2-17. Base Address Register for I/O space............................................................................................ 26

Table 2-18. Subsystem Vendor ID Register Layout ......................................................................................... 27

Table 2-19. Subsystem ID Register Layout ..................................................................................................... 27

Table 2-20. Capability Pointer Register Layout ............................................................................................... 27

Table 2-21. Interrupt Line Register Layout ...................................................................................................... 27

Table 2-22. Interrupt Pin Register Layout ........................................................................................................ 28

Table 2-23. MIN_GNT Register Layout ........................................................................................................... 28

Table 2-24. MAX_LAT Register Layout............................................................................................................ 28

Table 2-25. Power Management Interface Registers ...................................................................................... 29

Table 2-26. Capability ID0 Register for Power Management Interface Layout ............................................... 29

Table 2-27. Next Item Pointer0 Register Layout .............................................................................................. 29

Table 2-28. PMC Register Layout .................................................................................................................... 30

Table 2-29. PMCSR Layout ............................................................................................................................. 31

Table 2-30. Data Register ................................................................................................................................ 31

Table 2-31. Vital Product Data Registers ......................................................................................................... 33

Table 2-32. Capability ID1 Register Layout for Vital Product Data .................................................................. 33

Table 2-33. Next Item1 Pointer Register Layout .............................................................................................. 33

Table 2-34. VPD Address Register Layout ...................................................................................................... 34

Table 2-35. VPD Data Register Layout ............................................................................................................ 34

Table 2-36. CompactPCI Hot Swap Registers ................................................................................................. 35

Table 2-37. Capability ID2 Register Layout for CompactPCI Hot Swap .......................................................... 35

Table 2-38. Next Item Pointer2 Register Layout .............................................................................................. 35

Table 2-39. HS_CSR Layout ........................................................................................................................... 36

Table 3-1. DWORD Data path Endian Conversion .......................................................................................... 46