SB4002A_Data Sheet_EN

SB4002A

2.3 PCI Power Management Interface

In some cases, it is necessary to control the power supply of the PCI bus embedded system.

Especially for the mobile system which uses an independent power supply or the PCI device which

consumes a large amount of power, it is required to configure a low-power consuming system by

limiting power supply when the PCI device is not is operation. The PCI specification defines the

power management interface for easier power management.

For the control of power supply in the software level, the power management related registers are

located in the configuration I/O space header, and the address can be changed. In SB4002A, the

registers are in 40h~47h. In order to apply power management, you need to set the capability

pointer to 40h.

SB4002A supports PCI Power Management Interface Specification Revision 1.1. The following

tables show the registers contained in the configuration I/O space header.

PMCSRPMCSR_BSE

40h Capability ID0

Data

Next Item Ptr0PMC

44h

Table 2-25. Power Management Interface Registers

Capability ID0 Register

Power Management Interface ID

Table 2-26. Capability ID0 Register for Power Management Interface Layout

Capability ID for the Power Management Interface. The default is 01h. [RO : non-downloadable]

Next Item Point0 Register

Next Item Pointer0

Table 2-27. Next Item Pointer0 Register Layout

The pointer indicates the address of the register for the next capability. If there is no next capability, the

value must be 00h. [RO : downloadable]