SB4002A_Data Sheet_EN

SB4002A
25
BIST(Built-in Self Test) Register
BIST
Capable
6
Reserved
0
Start
5
Completion Code
4 37
BIST
Table 2-15. BIST Register Layout
This register is used to control BIST.
Bit[7] : The value 1b supports BIST, and 0b does not support BIST.
Bit[6] : The value 1b starts BIST. When the BIST is finished, the device resets BIST by writing 0b on this
bit.
Bit[5:4] : Reserved.
Bit[3:0] : The value 0b indicates that BIST is passed. Other values provide information on errors.
SB4002A does not support this bit. The default is 0b. [RO : non-downloadable]
Base Address Register0/1/2/3/4/5
Designates the base address for access of a device or a memory on the Local Bus. Bit[0] in all Base
Address Registers is read-only and used to determine whether the register maps into Memory or I/O
Space. [downloadable]
For Memory Space
3
Base Address 0
Memory Space Indicator
4
Type
Prefetchable
0231 1
Table 2-16. Base Address Register for Memory space
Bit[31:4] : This bit sets the base address of this Memory space. It is used by the address
decoder. [W/R]
Bit[2:1] : 00b indicates 32bit address space, and 10b indicates 64bit address space. The remaining values
are reserved. [RO]
Bit[0] : This bit indicates that Base Address Register maps Memory Space. [RO]