SB4002A_Data Sheet_EN

SB4002A

SB4002A does not support this bit. The default is 0b. [RO]

Bit[7] : Fast Back-to-Back Capable. The bit indicates whether the target device supports the fast back-to-

back transaction for a different device. 1b is support, and 0b is no-support. The default is 1b. [RO]

Bit[6] : Reserved. The default is 0b

Bit[5] : 66MHz Capable. The bit indicates whether the device supports 66MHz. 0b indicates that the

device supports 33MHz only, and 1b indicates that the device supports both 33MHz and 66MHz.

Because SB4002A supports 66MHz, the default is 1b. [RO]

Bit[4] : Capabilities List. The bit indicates if a new Capabilities Linked List Pointer is implemented on 34h

of the Configuration Space Header. The value 1b indicates that the Capability Linked List is

supported, and 0b indicates that it is not supported. [RO : downloadable]

Bit[3] : Interrupt Status. The bit indicates the interrupt status of a device or function. If the interrupt disable

of the command register is 0b and the interrupt status is 1b, INTx# of the device or the function is

asserted. The interrupt disable value 1b does not affect this bit. [RO]

Bit[2:0] : Reserved.

Revision ID Register

Revision ID

7 0

Table 2-10. Revision ID Register Layout

The register indicates the revision of the device. The revision ID is assigned by the manufacturer. [RO :

downloadable]

Class Code Register

Base Class

Programming Interface

8 715 023

Sub Class

Table 2-11. Class Code Register Layout

This register provides the description on the function implemented by the device. The register is divided into

Base Class, Sub Class and Programming Interface by bytes. The register can be set to the value defined in

the PCI bus specification. [RO : downloadable]