SB4002A_Data Sheet_EN

SB4002A
19
2.2 PCI Configuration Space Header
All PCI devices must implement Configuration Space Header. The Configuration Space Header
contains information on the device and the resources (base address space, interrupt, and etc.)
used by the device. At system booting or system configuration, BIOS or OS reads the
Configuration Space Header, runs P&P, and allocates the system resources.
This I/O space can be accessed by DWORD, WORD and BYTE. SB4002A responses for type0
access only.
The following table describes the details of the Configuration Space Header. SB4002A downloads
header information from the external serial ROM at booting.
Address
BYTE3
BYTE2
BYTE1
BYTE0
00h
Device ID
Vendor ID
04h
Status
Command
08h
Class Code
Revision ID
0Ch
BIST
Header Type
Latency Timer
Cache Line Size
10h
Base Address0 Register
14h
Base Address1 Register
18h
Base Address2 Register
1Ch
Base Address3 Register
20h
Base Address4 Register
24h
Base Address5 Register
28h
Cardbus CIS Pointer
2Ch
Subsystem ID
Subsystem Vendor ID
30h
Expansion ROM Base Address
34h
Reserved
Capabilities Ptr
38h
Reserved
3Ch
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Table 2-5. PCI Configuration Header Space