SB4002A_Data Sheet_EN

SB4002A

In the above figure, a transaction is started at CLK 1, CLK 2 and CLK 3. The target finds a critical

error at CLK 4, deasserts TRDY# and DEVSEL#, and asserts STOP#. At CLK 5, the master

checks this, recognizes Target-Abort, and deasserts FRAME#. At CLK 6, IRDY# and STOP# are

deasserted, and the transaction is terminated with Target-Abort.

2.1.7 PCI Parity Generation & Checking

In order to verify that address and data are transferred properly, PCI outputs the even parity signal

via PAR. The devices must output the even parity on AD[31:0]. In other words, the master outputs

the parity corresponding to the address phase and the data phase of the write transaction, and the

target outputs the parity corresponding to the data phase of the read transaction.

The even parity of AD [31:0] and C/BE [3:0]# are output on PAR. Even a meaningless value on

AD[31:0] must be included in the parity. The address parity is output on PAR for a clock after the

address phase. The data parity is output on PAR for a clock after a data phase with valid data, in

other words, after both IRDY# and TRDY# are asserted.

In figure 2-8, the master starts outputting the PAR for the address phase at CLK 2 and CLK 6, and

the PAR for the data phase for writing at CLK 7. The target starts outputting the PAR for the data

phase at CLK 4.

2.1.8 PCI Error Reporting

PCI enables the target to report transaction errors to the master.

PERR# is the error reporting signal output by the target for a data parity error, and SERR# is the

error reporting signal output for a critical error on the system.

For a write transaction, if the even parity is not consistent in PAR, AD [31:0] and C/BE[3:0]# from

the next clock after IRDY# is asserted, the target asserts PERR#. For a read transaction, if the

even parity is not consistent in PAR, AD [31:0] and C/BE[3:0]# from the next clock after TRDY# is

asserted, the master asserts PERR#. If PERR# is asserted, PERR# is maintained for two clocks

after the data phase is terminated.

SERR# is asserted if an address parity error occurs. If the even parity is not consistent between

PAR, the address value and the command value after the address phase, SERR# must be

asserted for the next one clock. SERR# is also asserted for other critical errors.

(* SB4002A supports the PERR# for the data parity error only. If an address parity error occurs, the

device disregards the transaction, and terminates the transaction with Master-Abort.)