SB4002A_Data Sheet_EN

SB4002A
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device. The device sets the DEVSEL timing of status register of the configuration space header
depending on the time point it can assert DEVSEL#. In the above figure, if DEVSEL# is asserted at
CLK 2, CLK 3 and CLK 4, it is set to FAST (00b), MEDIUM (01b) and SLOW (10b), respectively. If
no device has asserted DEVSEL# by CLK 4, the subtractive decoding device asserts DEVSEL#. If
the system has no subtractive decoding device, DEVSEL# is not asserted at CLK 4, and the
master terminates the transaction with Master Abort. (SB4002A supports MEDIUM.)
- In any case, a data transfer occurs if both TRDY# and IRDY# are asserted.
- Once TRDY# and IRDY# are asserted in a data phase, they cannot be deasserted by the end of
the data phase.
- In a data phase, C/BE[3:0]# means byte enable. It always has an effective value through the data
phase. Once a data phase is started, the value must not be changed. In a burst transfer, as soon
as a data phase is completed, the byte enable value for the next data phase is assigned on
C/BE[3:0]#.
2.1.6 PCI Target Termination
PCI bus provides the target termination, as well as the master termination which is provided by
other bus, in order to handle the situation that the target fails to execute the request of the master
or that it is necessary for the target to stop execution.
Target termination is divided into Retry, Disconnect and Target-Abort.
Retry
The target terminates transaction when it cannot perform the request of the master due to other
internal process. No data transfer occurs in this case, and the master must retry the request.
At the first data phase, the target asserts STOP# instead of TRDY# to execute retry. It also asserts
IRDY# and STOP# together to terminate the transaction with RETRY.
2
FRAME#
3 4
IRDY#
CLK
1 6
DEVSEL#
STOP#
TRDY#
5
Figure 2-4. Retry
In the above figure, a transaction is started normally at CLK 1 or CLK 2. If the target determines