SB4002A_Data Sheet_EN

SB4002A
13
FRAME# is asserted, a burst access occurs. At CLK 4, IRDY# and TRDY# are asserted at the
same time, and a data transfer occurs. As FRAME# is asserted, a burst access occurs. And as
IRDY# and TRDY# are deasserted, a wait cycle is inserted.
BE#'s-3
2
DATA
TRDY#
DATA-2
C/BE#
DATA-1
3
DATA
51 84
ADDRESS
6
DATA
ADDRESS
FRAME#
IRDY#
9
PHASE PHASE
BE#'s-2BUS CMD BE#'s-1
CLK
PHASE
DEVSEL#
AD
7
DATA-3
PHASE
Figure 2-2. PCI BUS Basic Write Transaction
At CLK 5, the master device asserts IRDY#, indicating that it is ready to transfer data, while TRDY#
keeps deasserted. The target extends the wait cycle. At CLK 8, the target asserts TRDY#,
indicating that it is ready to transfer data. At CLK 9, IRDY# and TRDY# are asserted at the same
time, and a data transfer occurs. As FRAME# is deasserted, the transaction is terminated. The
master deasserts IRDY# and the target deasserts TRDY# and DEVSEL#. Therefore a PCI bus
write transaction is completed.
The following rules are applied to the basic transaction.
- The point that DEVSEL# is asserted depens on the characteristics of the target (Refer to config).
2 81 7
FRAME#
5
SUB
DEVSEL#
3
SLOWMEDIUM
IRDY #
64
CLK
TRDY#
FAST
Figure 2-3. DEVSEL# timing
The above figure shows the points DEVSEL# is asserted depending on the characteristics of the