SB4002A_Data Sheet_EN

SB4002A

As Frame# is asserted, a burst access occurs. Because IRDY# is deasserted, a wait cycle is

inserted by the master.

At CLK 7, IRDY# is reasserted, and a data transfer occurs at CLK 8. At this point, because

FRAME# is deasserted, the transaction is terminated. The master deasserts IRDY#, and the target

deasserts TRDY# and DEVSEL#. Therefore a PCI BUS read transaction is completed.

ADDRESS

IRDY#

DATA-1

TRDY #

942

DATADATA

DATA-3

FRAME#

ADDRESS

CLK

BE#'s

PHASE

DATA-2

C/BE#

BUS CMD

PHASE

DEVSEL#

PHASE PHASE

DATA

Figure 2-1. PCI BUS Basic Read Transaction

Write Transaction

The address phase is processed in the same way as in the read transaction. In the write

transaction, because the master outputs the signal on AD [31:0] at both the address phase and the

data phase, unlike the read transaction, no turn around cycle is required. The data phase may be

completed right after the address phase depending on the capability of the master and the target.

The data phase is also the same as that in the read transaction, except that the master outputs

data on AD[31:0] in the write transaction. When the data is ready, the master outputs the data on

AD [31:0] and asserts IRDY#. If the target is prepared to receive the data, i.e. TRDY# is asserted,

the data transmission is completed and the data phase is terminated. This process is repeated until

FRAME# is deasserted when a data transfer is completed, which means it is the last data phrase.

In this case TRDY#, IRDY# and DEVSEL# are all deasserted and a transaction is terminated.

In Figure 2-2, the master device starts PCI bus transaction at CLK 1. At this point, as the address

phase is started, the master asserts FRAME#, outputs the address on AD, and asserts the WRITE

command on C/BE#.

At CLK 2, the target reads and decodes the address and command, and asserts DEVSEL# to

indicate that the target is selected. The master device asserts IRDY# and the target device asserts

TRDY#, indicating that they are prepared to transfer data.

At CLK 3, IRDY# and TRDY# are asserted at the same time, and a data transfer occurs. As