SB4002A_Data Sheet_EN

SB4002A

Configuration Space of the intended target. Because SB4002A supports the single function only,

only Function Number 0 is available. For accessing Configuration Space, SB4002A supports the

IDSEL signal 1 only in the address phase.

2.1.5 PCI Basic Transaction

All the functions specified below are based on the rising edge of CLK.

Read Transaction

All transactions are triggered as FRAME# is asserted. The bus master outputs the address on AD

[31:0] and the command on C/BE [3:0]# as it asserts FRAME#. For Configuration Space access,

the bus master outputs 1 on IDSEL. This is called as address phase. Only 1 clock is maintained for

address phase. The target shall receive and decode address, command and IDSEL. The selected

target shall assert DEVSEL# to notify the master of its selection. The data phrase starts at Address

phase.

In the read transaction, the target outputs the signal on AD [31:0] and the master receives the

signal, which is the contrary to the address phase. Therefore, it is required to insert the turn around

cycle by deasserting TRDY# for at least one clock. If the data requested by the master is prepared,

the target outputs the data on AD[31:0], and asserts TRDY#. If the master is ready to receive the

data, i.e. IRDY# is asserted, the data transmission is terminated and the data phase is over. If

FRAME# is asserted instead of IRDY#, which means that the transaction is not terminated and the

burst is in progress, the target outputs the data on AD [31:0] and asserts TRDY#. When the master

is prepared to receive the data, IRDY# is asserted and the data transmission is terminated.

This process is repeated until FRAME# is deasserted when both TRDY# and IRDY# are asserted

at the same time and the data transmission is completed. In this case, TRDY#, IRDY# and

DEVSEL# are all deasserted and a transaction is terminated.

In Figure 2-1, the master device starts transaction of PCI bus at CLK 1.

At this point, as the address phase is started, the master asserts FRAME#, outputs the address on

AD, and asserts the READ command on C/BE#. The target device reads the address and the

command at CLK2, and prepares a transaction. A turnaround cycle is inserted at CLK 2. The

master device asserts IRDY#, indicating that it is ready to transfer data.

At CLK 3, the target device asserts DEVSEL# to indicate its selection, and asserts TRDY# and

outputs the read data on AD to indicate that it is ready to transfer data,

At CLK 4, IRDY# and TRDY# are asserted at the same time, and a data transfer occurs. As

FRAME# is asserted, a burst access occurs. And as TRDY# is deasserted, a wait cycle is inserted

by the target.

At CLK 5, the target reasserts TRDY#, indicating that it is ready to transfer data. At CLK 6, IRDY#

and TRDY# are asserted at the same time, and a data transfer occurs.