SB4002A_Data Sheet_EN

SB4002A

Out of the commands mentioned in the above table, SB4002A does not support Interrupt

Acknowledge, Special Cycle, Dual Address Cycle and the reserved commands. It does not

support Memory Read Multiple, Memory Read Line, and Memory Write and Invalidate Command

as well as SB4002A disregards the commands which are not supported.

2.1.4 PCI Addressing

I/O Space Addressing

In the I/O Address Space, all 32 AD lines(AD[31:0]) are used to provide a full byte address.

The following table shows the starting byte and BE# [3:0] in the data phrase depending on the

value of AD [1:0].

AD[1:0]

Starting Byte

BE#[3:0] Combinations

Byte 0

xxx0 or 1111

Byte 1

xx01 or 1111

Byte 2

x011 or 1111

Byte 3

0111 or 1111

Table 2-3. PCI Bus I/O Addressing Rule

If the above combination is not satisfied, SB4002A disregards the command.

Memory Space Addressing

In the Memory Address Space, accesses are decoded to a DWORD address using AD[31:2].

AD[1:0] determines the method of address increment for burst access. SB4002A supports the

linear incrementing only (00), and disconnect others after the first transmission.

Configuration Space Addressing

In the Configuration Address Spaces, accesses are decoded to a DWORD address using AD[7:2].

Configuration Space Addressing is divided into type0 and type1. Type1 is supported in the PCI-to-

PCI bridge device only, and is disregarded in SB4002A. The following table shows the

Configuration Space addressing of type0.

31 11

10 8

7 2

1 0

Reserved

Function Number

Number

Table 2-4. PCI Configuration Space Addressing

Function Number is an encoded value used to select one of eight possible functions on a

multifunction device. Register Number is an encoded value used to index a DWORD in