SB16C1058PCI_Data Sheet_EN
SB16C1058PCI
PCI Target Interface Controller
with Octal-UART
JULY 2013 REV 1.04
13
Table 6–1: Pin Description…continued
Serial EEPROM Interfaces
Name
Pin
Type
Description
RCS
125
O
Serial EEPROM Chip Select: Connected to CS of serial EEPROM.
RSK
124
O
Serial EEPROM Data Clk: Connected to SK of serial EEPROM.
RDI
123
O
Serial EEPROM Data Input: Connected to DI of serial EEPROM.
RDO
122
I
Serial EEPROM Data Output: Connected to DO of serial EEPROM.
PCI Interfaces
Name
Pin
Type
Description
CLK
49
I
PCI Clock: PCI clock provides timing for all transaction on SB16C1058PCI.
RESET#
51
I
PCI Reset: Reset the SB16C1058PCI. The inputted signal indicates when the
applied main power is within the specified tolerance and stable. This signal is
asynchronous to CLK when asserted or deasserted.
INTA#
50
O/D
Interrupt A: Interrupt A is used to request an interrupt. Interrupts on PCI are
defined as “level sensitive”, asserted low, using open drain output drivers. The
assertion and deassertion of INTA# is asynchronous to CLK.
PME#
52
O/D
Power Management Event: This signal can be used by SB16C1058PCI to
request a change in the SB16C1058PCI or main system power state. The
assertion and deassertion of PME# is asynchronous to CLK. This signal has
additional electrical requirements over and above standard open drain signals
that allow it to be shared between devices that are powered off and those that
are powered on. The use of this pin is specified in the PCI Bus Power
Management Interface Specification.
AD[31], AD[30]
AD[29], AD[28]
AD[27], AD[26]
AD[25], AD[24]
AD[23], AD[22]
AD[21], AD[20]
AD[19], AD[18]
AD[17], AD[16]
AD[15], AD[14]
AD[13], AD[12]
AD[11], AD[10]
AD[09], AD[08]
AD[07], AD[06]
AD[05], AD[04]
AD[03], AD[02]
AD[01], AD[00]
53, 54
55, 56
59, 60
61, 62
65, 66
67, 68
69, 70
71, 72
96, 97
98, 99
100,103
104,105
107,108
109,110
111,112
113,114
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
T/S
Address and Data: These signals are multiplexed on the same pins. A Bus
transaction consists of an address phase followed by a data phase.
SB16C1058PCI does no support both read and write bursts.