SB16C1058_Data Sheet_EN

SB16C1058
OCTAL UART WITH 256-BYTE FIFO
JULY 2013 REV 1.04
65
RXDx
t
RXRDY#
rint
(RD RBR)
IOR#
Clock
Sample
sint
t
STOP
(FIRST BYTE)
Figure 17: Receiver Ready Mode 0 Timing
Sample
sint
REACHES THE
RXDx
t
TRIGGER LEVEL)
t
IOR#
rint
RXRDY#
Clock
(FIRST BYTE THAT
STOP
(RD RBR)
Figure 18: Receiver Ready Mode 1 Timing
sim
RTSx#, DTRx#
(WR MCR)
t
t
rim
tt
simrim
t
sim
t
IOW#
m do
(RD MSR)
m do
IOR#
t
INTx
CTSx#, DSRx#, DCDx#
RIx#
Figure 19: Modem Control Timing